We need highly skilled Physical Design engineers who have experience with Synopsys 3D IC Compiler or Cadence Integrity 3D IC for enabling high-speed chip implementations, reducing power, increasing performance and optimizing silicon area.
The candidate will have good knowledge of 3D/2.5D Silicon Design & packaging with good understanding of Implementation, Signal Integrity, EMIR and lower node 3D IC design rules
The selected candidate will work on silicon realizations, partnering with logic designers and physical implementation engineers.
You will be responsible for Logic Synthesis, Physical Design, Power optimization, Timing Analysis, and flows for 5nm/3nm semiconductor products. You will work with a global team through the entire silicon development cycle till tapeout
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