Senior ASIC Physical Design Engineer - GenAI Job at USA Tech Recruit, San Jose, CA

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  • USA Tech Recruit
  • San Jose, CA

Job Description

Senior ASIC Physical Design Engineer - GenAI

📍 Location: San Jose, CA (Hybrid options available)

Are you an experienced ASIC Physical Design Engineer looking for your next challenge? Join a cutting-edge company at the forefront of AI-driven innovation, working on high-performance, low-power AI inference acceleration solutions. We are a well-funded startup with a global presence, offering the chance to work with top talent in a fast-paced, collaborative environment.

What You'll Do:

🔹 Lead ASIC front-end physical design and workflow development for next-gen AI inference acceleration products

🔹 Optimize and implement synthesis, formal verification, power analysis, and STA workflows

🔹 Collaborate closely with design and verification teams to improve workflows and EDA tool efficiency

🔹 Contribute to scalable, high-performance ASIC development, using leading EDA tools (Cadence, Synopsys, etc.)

What We're Looking For:

✔ 10+ years of ASIC engineering experience, including VLSI/SoC physical design workflows

✔ Hands-on expertise with STA analysis, SDC writing, clock methodology, and power analysis

✔ Ability to collaborate with backend teams on clock trees, routing, DRC, LVS, and tapeout

✔ Strong problem-solving skills and ability to work in a fast-paced, startup environment

✔ Bachelor’s or Master’s in Computer Science, Electrical Engineering, or related field

Why Join Us?

✨ Be part of a growing, innovative company shaping the future of AI acceleration

✨ Work alongside top industry experts in a dynamic, high-impact role

✨ Competitive salary, equity, and benefits (Medical, Vision, Dental, Flexible PTO)

✨ Perks like meals, snacks, flexible work hours, and a vibrant office culture

Ready to make an impact? Apply now or reach out for more details! 🚀

Job Tags

Flexible hours,

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