Job Description

Our client, a leading semiconductor giant, is seeking a Senior Physical Design Engineer for a FullTime - Onsite opening in Sunnyvale, CA.

Role: Physical Design Engineer

Location: Sunnyvale, CA (Onsite)

Full-Time Only

Visa: No OPT/CPT

H1B Transfer is okay

• Physical Design Engineering Services
• Design and implementation of physical design (“PD”) flows, including and not limited to: Synthesis, Place and Route, Clock Tree Synthesis, Power Grid design, Static Timing Analysis, Design Rule Check, Layout vs. Schematic, and ECO flow Execution of PD flows on various blocks including SoC subsystems, IPs, sub-IPs, modules, and library components
• Need exp in CAD methodology
• Timing closure, power, and area optimization
• Signoff and chip finishing (DRC/LVS) at block / SoC level Implementation of multi-voltage physical designs featuring multiple power domains and power gating (using UPF), clock domains and clock gating, clock and power domain crossing, and other low power PD techniques
• Develop RTL2GDS flows and methodologies by exploring different EDA tools and process technologies for efficient execution of multiple PD tasks to get the best PPA

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